Microprocessor & Assembly Language

┌─────────────────────────────────────────────────────────────────┐
│                      8086 MICROPROCESSOR                        │
├──────────────────────────┬──────────────────────────────────────┤
│   BUS INTERFACE UNIT     │        EXECUTION UNIT                │
│         (BIU)            │            (EU)                      │
├──────────────────────────┼──────────────────────────────────────┤
│  ┌────────────────────┐  │  ┌──────────────────────────────┐   │
│  │ Address Adder (Σ)  │  │  │   Control Circuitry          │   │
│  │ PA = Seg×10H+Off   │  │  │   Instruction Decoder        │   │
│  └────────────────────┘  │  └──────────────────────────────┘   │
│                          │                                      │
│  ┌────────────────────┐  │  ┌──────────────────────────────┐   │
│  │ Segment Registers  │  │  │ General Purpose Registers    │   │
│  │ CS, DS, SS, ES     │  │  │ AX, BX, CX, DX              │   │
│  └────────────────────┘  │  │ SP, BP, SI, DI               │   │
│                          │  └──────────────────────────────┘   │
│  ┌────────────────────┐  │                                      │
│  │ IP (Instruction    │  │  ┌──────────────────────────────┐   │
│  │     Pointer)       │  │  │        ALU (16-bit)          │   │
│  └────────────────────┘  │  └──────────────────────────────┘   │
│                          │                                      │
│  ┌────────────────────┐  │  ┌──────────────────────────────┐   │
│  │ 6-Byte Instruction │  │  │      Flag Register           │   │
│  │     Queue (FIFO)   │  │  │   (9 active flags)           │   │
│  └────────────────────┘  │  └──────────────────────────────┘   │
└──────────────────────────┴──────────────────────────────────────┘

Functions:

Given: DS=7000H, ES=1550H, SI=0050H, DI=0020H

When DF=0 (Increment Mode):

• Source: ES×10H + SI = 15500H + 0050H = 15550H
• Destination: DS×10H + DI = 70000H + 0020H = 70020H
• After: SI=0052H, DI=0022H (incremented by 2)

When DF=1 (Decrement Mode):

• Source: ES×10H + DI = 15500H + 0020H = 15520H
• Destination: DS×10H + SI = 70000H + 0050H = 70050H
• After: SI=004EH, DI=001EH (decremented by 2)

; DF=0 (Increment)
CLD              ; Clear direction flag
LEA SI, SOURCE
LEA DI, DEST
MOVSB            ; SI++, DI++

; DF=1 (Decrement)
STD              ; Set direction flag
LEA SI, SOURCE+1
LEA DI, DEST+1
MOVSB            ; SI--, DI--

Physical Address is the 20-bit actual address generated by BIU to access memory.

Example: CS=348AH, IP=4214H → PA = 348A0H + 4214H = 38AB4H

Relative Addressing: Operand is signed 8-bit displacement relative to PC/IP.

; JNC - Jump if No Carry
JNC START    ; If CF=0, jump to START

; JNZ - Jump if Not Zero  
JNZ NEXT     ; If ZF=0, jump to NEXT

Given: Initial SP=40C5H, SS=2022H

After PUSH:

• SP = SP - 2 = 40C3H
• [40C3H] = low byte, [40C4H] = high byte

After POP:

• SP = SP + 2 = 40C5H (restored)

• CS + IP = Program execution address
• DS + SI/DI/BX = Data access address
• SS + SP/BP = Stack access address

• 6-byte FIFO instruction queue in BIU
• Pre-fetches instructions ahead of execution
• Enables pipelining - fetch while executing
• Resets on Jump/Call instructions
• Removes instructions when EU reads them

MOV AH, 55H    ; AH = 55H
MOV AL, 01H    ; AX = 5501H
MOV CX, 01FAH  ; CX = 01FAH
MUL CL         ; AX = 01H × FAH = 00FAH
DIV CH         ; AX = 00FAH ÷ 01H = 00FAH

Final AX = 00FAH

MOV AX, [BX] - Reads from DS:BX (16-bit)

MOV [BP], DL - Writes to SS:BP (8-bit)

Addressing Modes are the different ways the processor determines the effective address (EA) of an operand. The 8086 supports 12 addressing modes in 5 groups:

Analysis: Arithmetic series with a=5, d=5, last term=125. Number of terms = 125/5 = 25. Loop count = 25−1 = 24 (18H).

; Sum = 5+10+15+...+125
; Series: a=5, d=5, last=125, n=25, additions=24

        MOV CX, 18H      ; CX = 24 (loop counter)
        MOV AX, 0005H    ; AX = first term (5)
        MOV BX, 000AH    ; BX = second term (10)

NEXT:   ADD AX, BX       ; AX = AX + BX (accumulate sum)
        ADD BX, 0005H    ; BX = next term (+5)
        DEC CX           ; CX = CX - 1
        JNZ NEXT         ; If CX ≠ 0, jump to NEXT

; After loop: AX = 1625 (decimal sum)
; Store result
        MOV [RESULT], AX
        HLT

RESULT  DW 0             ; Memory location for result

MOV BX, [SI] — Memory Read (Data Transfer from Memory to Register)

MOV [DL], AL — I/O Write (Data Transfer from Register to I/O Port)

Note: DL contains the 8-bit port address. This is an I/O write operation.

DEN (Data Bus Enable) — Pin 26

DEN is an active-low output signal in minimum mode. When low, it enables external data bus transceivers/buffers. It goes active during data transfer phases of bus cycles and inactive during address phases. This prevents data bus contention when address and data share the same multiplexed bus (AD15-AD0).

NMI (Non-Maskable Interrupt) — Pin 17

NMI is a edge-triggered (low-to-high) interrupt input. Unlike INTR, NMI cannot be disabled by clearing IF (Interrupt Flag). It is always serviced. When NMI is activated, the processor completes the current instruction, saves flags (push), clears IF and TF, then fetches the interrupt service routine from vector address 00008H (vector 2). Used for critical events like power failure, memory parity errors.

Status Bus (A19/S6 – A16/S3)

These are multiplexed address/status pins. During T1 of a bus cycle, they carry the upper 4 address bits (A19-A16). During T2-T4, they output status information:

S5 = IF (Interrupt Flag status), S6 = 0 (always low).

DT/R (Data Transmit/Receive) — Pin 27

DT/R is an output signal in minimum mode that controls the direction of external data bus transceivers.

• DT/R = 1 (Transmit): CPU is writing data to memory or I/O (data flows out from CPU).
• DT/R = 0 (Receive): CPU is reading data from memory or I/O (data flows into CPU).

This signal must be connected to the direction control pin of external bus transceivers (like 74LS245) to ensure correct data flow direction.

Accumulator — AX Register

AX (16-bit) is called the accumulator. It is split into AH (high byte) and AL (low byte). Special uses:

• I/O Operations: IN and OUT instructions must use AL (8-bit) or AX (16-bit) as the data register.
• MUL/DIV: MUL multiplies AL (or AX) by operand, result in AX (or DX:AX). DIV divides AX (or DX:AX) by operand.
• String I/O: LODS loads from [DS:SI] into AL/AX. STOS stores AL/AX to [ES:DI]. SCAS compares AL/AX with [ES:DI].
• BCD Adjustments: DAA and DAS adjust AL after BCD addition/subtraction.
• Sign Extend: CBW extends AL to AX (sign). CWD extends AX to DX:AX.

CX Register — Count Register

CX (16-bit) is split into CH (high byte) and CL (low byte). Special uses:

• LOOP Instruction: CX is automatically decremented by 1. Loop jumps to label if CX ≠ 0.
• LOOPZ/LOOPNZ: Conditional loop using CX as counter with zero-flag check.
• REP Prefix: Repeats string instruction CX times (REP MOVSB, REP LODSB, etc.).
• Shift/Rotate Count: CL register specifies the count for shift and rotate instructions (SHR, ROL, etc.).
• String Scan: REPNE SCASB scans memory CX times comparing with AL.

The 8254 uses A1 and A0 (connected to system address lines) to select between its internal registers. CS (chip select) is typically decoded from higher address lines (e.g., A15 inverted).

Address Selection Table (A1, A0):

If CS is decoded from A15 (inverted, active low), then:

• A15 = 0 for 8254 selected (address range 0000H–7FFFH)
• A14-A2 are decoded to select the specific 8254 in a multi-device system
• A1 and A0 select the internal register

Control Word Calculation:

Counter 1, Mode 4, Binary count, LSB+MSB write:

Count Value:

65000 decimal = FE60H (16-bit binary)

LSB = 60H, MSB = FEH

Subroutine:

; Initialize Counter 1 in Mode 4, Count = 65000
; Assumes: Control Register = 8003H, Counter 1 = 8001H

INIT_CTR1 PROC NEAR
    ; Step 1: Write Control Word
    MOV AL, 78H         ; 01 11 100 0 = Counter1, LSB+MSB, Mode4, Binary
    OUT 8003H, AL       ; Write to Control Register

    ; Step 2: Load count LSB first
    MOV AL, 60H         ; Low byte of FE60H
    OUT 8001H, AL       ; Write to Counter 1

    ; Step 3: Load count MSB
    MOV AL, FEH         ; High byte of FE60H
    OUT 8001H, AL       ; Write to Counter 1
    RET
INIT_CTR1 ENDP

; Read Count on the Fly (without stopping counter)
READ_CTR1 PROC NEAR
    ; Step 1: Write Latch Command for Counter 1
    MOV AL, 40H         ; 01 00 0000 = Latch Counter 1
    OUT 8003H, AL       ; Write to Control Register

    ; Step 2: Read LSB first
    IN AL, 8001H        ; Read LSB of latched count
    MOV BL, AL          ; Store in BL

    ; Step 3: Read MSB
    IN AL, 8001H        ; Read MSB of latched count
    MOV BH, AL          ; Store in BH
    ; BX now contains the latched count value
    RET
READ_CTR1 ENDP

Explanation:

• Latch Command (40H): Freezes the current count in an internal latch so it can be read without affecting the counting process.
• Read Order: Always read LSB first, then MSB (matching the write order set in the control word).
• GATE Pin: Must be high (logic 1) for the counter to count in Mode 4.

Timing Calculation:

Assume CLK = 3.5 MHz (typical for 8086 system):

Main Program:

; Main Program: Display seconds on 7-segment or counter
; Counter 1 in Mode 4, Count = 65000
; CLK = 3.5 MHz, ~18.57ms per countdown

COUNTS_PER_SEC  EQU 54      ; 54 calls ≈ 1 second
DISP_COUNT      DB 0        ; Seconds counter (0-59)

MAIN:
    MOV AX, 0000H
    MOV DS, AX              ; Initialize DS

    ; Initialize Counter 1
    CALL INIT_CTR1          ; From Q6b subroutine

SECOND_LOOP:
    MOV CH, COUNTS_PER_SEC  ; CH = 54 (calls per second)

WAIT_SEC:
    ; Wait for Counter 1 countdown to complete
    CALL READ_CTR1          ; Read current count
    CMP BX, 0000H           ; Check if counter reached 0
    JNZ WAIT_SEC            ; Keep polling

    ; Counter finished one cycle, reinitialize
    CALL INIT_CTR1

    DEC CH                  ; One more 18.57ms passed
    JNZ WAIT_SEC            ; Continue until 54 calls

    ; 1 second elapsed
    INC DISP_COUNT          ; Increment seconds display
    CMP DISP_COUNT, 60      ; Check if 60 seconds
    JL DISPLAY_SEC

    MOV DISP_COUNT, 0       ; Reset to 0 (optional: increment minutes)

DISPLAY_SEC:
    MOV AL, DISP_COUNT
    ; Output to display port (e.g., 7-segment decoder)
    OUT 80H, AL             ; Write to display port

    JMP SECOND_LOOP         ; Repeat forever

Alternative: Using Mode 2 (Rate Generator) for continuous seconds:

; Cascade: Counter 1 (Mode 2, count 50000) drives Counter 2 (Mode 2, count 40)
; Total: 50000 × 40 = 2,000,000 counts = 1 second at 2MHz

; Counter 1 Control Word: 01 11 010 0 = 74H
; Counter 2 Control Word: 10 11 010 0 = 94H

INIT_SECONDS PROC NEAR
    ; Counter 1: Mode 2, Count = 50000
    MOV AL, 74H
    OUT 8003H, AL
    MOV AL, 50H             ; LSB of 50000 (C350H)
    OUT 8001H, AL
    MOV AL, C3H             ; MSB
    OUT 8001H, AL

    ; Counter 2: Mode 2, Count = 40
    MOV AL, 94H
    OUT 8003H, AL
    MOV AL, 28H             ; 40 = 28H
    OUT 8002H, AL
    MOV AL, 00H
    OUT 8002H, AL

    RET
INIT_SECONDS ENDP

┌─────────────────────────────────────────────────────────────────────┐
│                         8254 TIMING COUNTER                         │
├─────────────────────────────────────────────────────────────────────┤
│                                                                     │
│   D7-D0 ──>┌─────────────────┐                                     │
│  (Data Bus) │   Data Bus      │                                     │
│             │   Buffer        │                                     │
│             └────────┬────────┘                                     │
│                      │ Internal Bus                                  │
│   RD ──>  ┌─────────┴─────────┐  <── WR                            │
│   CS ──>  │  Read/Write Logic  │  <── A0, A1                        │
│            └─────────┬─────────┘                                     │
│                      │                                               │
│            ┌─────────┴─────────┐                                     │
│            │ Control Word      │                                     │
│            │ Register          │                                     │
│            └─────────┬─────────┘                                     │
│                      │                                               │
│   ┌──────────────────┼──────────────────┐                           │
│   │                  │                  │                           │
│   ▼                  ▼                  ▼                           │
│ ┌──────┐        ┌──────┐          ┌──────┐                          │
│ │CTR 0 │        │CTR 1 │          │CTR 2 │                          │
│ │      │        │      │          │      │                          │
│ │CLK0  │        │CLK1  │          │CLK2  │                          │
│ │GATE0 │        │GATE1 │          │GATE2 │                          │
│ │OUT0  │        │OUT1  │          │OUT2  │                          │
│ └──────┘        └──────┘          └──────┘                          │
│                                                                     │
│   CLK  ──> 16-bit Counter ──> OUT (3 independent channels)         │
│   GATE ──> Gate Control (starts/stops counting)                    │
└─────────────────────────────────────────────────────────────────────┘

Block Diagram Components:

Applications of 8254:

• Real-Time Clock: Generate periodic interrupts for timekeeping (e.g., 100 Hz for OS tick).
• Event Counter: Count external events using CLK input (Mode 0).
• Digital One-Shot: Generate a single pulse of programmable width (Mode 1).
• Square Wave Generator: Generate precise frequency square waves (Mode 3).
• Rate Generator: Generate periodic pulses at specified intervals (Mode 2).
• Complex Waveform Generator: Combine multiple modes for audio/signal generation.
• DRAM Refresh: Generate DMA request signals for periodic DRAM refresh.
• Baud Rate Generator: Provide clock for serial communication.

Key Features (8254 vs 8253):

Read-Back Command (8254 only, not 8253)

The read-back command allows the CPU to read both the count value and status of multiple counters simultaneously using a single command byte.

Read-Back Command Format:

D7  D6  D5  D4  D3  D2  D1  D0
 1   1   COUNT STATUS CNT2 CNT1 CNT0  0
 │   │    │     │      │    │    └── Select Counter 0
 │   │    │     │      │    └─────── Select Counter 1
 │   │    │     │      └─────────── Select Counter 2
 │   │    │     └───────────────── Read status register
 │   │    └─────────────────────── Read count value
 │   └────────────────────────── Must be 1 for read-back
 └────────────────────────────── Must be 11 for read-back

• COUNT bit (D4): If 1, latches the count of selected counters for reading.
• STATUS bit (D3): If 1, latches the status register of selected counters.
• CNT2/CNT1/CNT0: Select which counters to read back (multiple can be selected).

Status Register Format:

D7  D6  D5  D4  D3  D2  D1  D0
OUTPUT NULLCOUNT RW1 RW0 M2 M1 M0 BCD
   │      │       └──────────┘  └─── BCD/Binary
   │      └──── If 1, count not yet loaded
   └─────────── Current OUT pin state

Count on the Fly (Reading While Counting)

To read the current count without stopping the counter (GATE must remain high):

1. Method 1 — Latch Command: Write counter latch command (SC1 SC0 0 0 X X X X) to freeze count. Then read LSB then MSB from counter port.
2. Method 2 — Read-Back Command: Write read-back command with COUNT=1. This latches count and optionally status. Then read status (if latched) then count (LSB then MSB).

; Method 1: Latch Command for Counter 0
MOV AL, 00H          ; 00 00 0000 = Latch Counter 0
OUT CTRL_REG, AL      ; Write latch command
IN AL, CTR0_PORT      ; Read LSB
MOV BL, AL
IN AL, CTR0_PORT      ; Read MSB
MOV BH, AL            ; BX = latched count

; Method 2: Read-Back Command for Counter 1
MOV AL, 0C6H          ; 11 11 0 1 1 0 0 = Read-back Counter1
OUT CTRL_REG, AL      ; Count + Status
IN AL, CTR1_PORT      ; Read status first
IN AL, CTR1_PORT      ; Read LSB of count
IN AL, CTR1_PORT      ; Read MSB of count

Mode 2: Rate Generator

Generates a continuous series of 1-clock-wide negative pulses at a programmable rate.

Mode 2 Waveform (N=5):

CLK:  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐
      └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘

OUT:  ──────────────────────────────┐     ┌─────────────────
      ↑ N-1=4 cycles high          └─────┘ 1 cycle low
                                  (auto-reload, repeats)

Mode 4: Software Triggered Strobe

Generates a single negative pulse (1 clock wide) after a software-triggered countdown. Unlike Mode 2, it does NOT auto-reload.

Mode 4 Waveform (N=5):

CLK:  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐  ┌──┐
      └──┘  └──┘  └──┘  └──┘  └──┘  └──┘  └──┘

OUT:  ──────────────────────────────┐     ─────────────────
      ↑ N=5 cycles high            └───── 1 cycle low
      (one-shot, stops — must reload)

Key Differences:

Mode 5: Hardware Triggered Strobe (for comparison)

Similar to Mode 4, but counting is triggered by a rising edge on the GATE pin (hardware trigger) instead of software loading. Useful when precise timing relative to an external event is needed.