Predicted Questions - Microprocessor Exam

Question Type	Marks	Frequency
Architecture Diagram + Functions	4-5	95%
Address Calculation	3-5	95%
Define Term (1-liner)	1	95%
Explain with Example	2-3	95%
Stack PUSH/POP Operation	5	85%
Find Instruction Errors	3	85%
Register Evaluation	5	85%
Compare Instructions	3	75%
Series Sum Program	5	75%

1a Compare BIU and EU with their functions 4 marks

📄 Page 4-6 | Pattern: Architecture (95% likely)

Feature	BIU	EU
Function	Fetches instructions	Executes instructions
Components	Segment registers, IP, Queue	ALU, Registers, Flags
Address	20-bit physical address	16-bit offset address

Feature	BIU (Bus Interface Unit)	EU (Execution Unit)
Full Form	Bus Interface Unit	Execution Unit
Main Function	Fetches instructions, reads/writes data from/to memory and I/O	Decodes and executes instructions, performs arithmetic/logic operations
Components	Segment registers (CS,DS,SS,ES), IP, 6-byte Queue, Address adder	ALU, General purpose registers, Flag register, Control unit
Address Generation	Generates 20-bit physical address using PA = Segment × 10H + Offset	Generates 16-bit offset address (Effective Address)
Queue	Contains 6-byte pre-fetch instruction queue (FIFO)	Reads instructions from the queue
Operation	Handles all bus operations and external interfacing	Controls internal operations and instruction execution

💡 Key Point: BIU and EU work simultaneously - BIU fetches while EU executes (pipelining).

1b If CS=2000H, IP=1500H, DS=3000H, BX=1000H, calculate physical address for instruction fetch and data access 3 marks

📄 Page 17-18 | Pattern: Address calc (95% likely)

Instruction: PA = 20000H + 1500H = 21500H

Data: PA = 30000H + 1000H = 31000H

1c Define offset address 1 mark

📄 Page 17 | Pattern: Define term (95% likely)

Offset Address is the 16-bit displacement within a segment.

1d Explain direct addressing mode with example 2 marks

📄 Page 29-30 | Pattern: Explain (95% likely)

Direct Addressing: Effective address is given directly in instruction.

MOV AX, [1000H]  ; Load from DS:1000H

2a Draw flag register of 8086 and explain any 5 flags 5 marks

📄 Page 10-14 | Pattern: Flags (85% likely)

Flags: OF DF IF TF SF ZF AF PF CF

Flag	Meaning
CF	Carry out of MSB
ZF	Result is zero
SF	MSB of result (sign)
OF	Signed overflow
DF	String direction (0=inc, 1=dec)

Flag Register Layout (16-bit):
BIT: 15  14  13  12  11  10   9   8   7   6   5   4   3   2   1   0
      U   U   U   U  OF  DF  IF  TF  SF  ZF   U  AF   U  PF   U  CF

Flag	Name	Description
CF	Carry Flag	Set by carry out of MSB in addition or borrow in subtraction
ZF	Zero Flag	Set if result is zero
SF	Sign Flag	Set if MSB of result is 1 (negative number)
OF	Overflow Flag	Set when signed result overflows destination capacity
DF	Direction Flag	Controls string direction: 0=auto-increment SI/DI, 1=auto-decrement
IF	Interrupt Enable	1=enable maskable interrupts, 0=disable
TF	Trap Flag	1=single step mode (debug)
AF	Auxiliary Carry	Carry between bit 3 and 4 (BCD operations)
PF	Parity Flag	Set if lower byte has even number of 1s

💡 Remember: CP AZS are status flags (conditional), DIT are control flags.

2b Find errors: (i) ADD AX, BL (ii) MOV CS, AX (iii) MUL 100H 3 marks

📄 Page 28, 37 | Pattern: Errors (85% likely)

Instruction	Error
`ADD AX, BL`	Size mismatch (16 vs 8 bit)
`MOV CS, AX`	CS can't be destination
`MUL 100H`	Immediate not allowed

Instruction	Error	Correct Form
`ADD AX, BL`	Size mismatch - can't mix 16-bit and 8-bit registers	`ADD AL, BL` or `ADD AX, BX`
`MOV CS, AX`	Code Segment register cannot be destination in MOV instruction	`MOV DS, AX`
`MUL 100H`	MUL operand must be register or memory, not immediate value	`MOV BX, 100H` then `MUL BX`

💡 Key Rules: No size mismatch, CS ≠ destination in MOV, MUL/IMUL needs register/memory operand.

2c What is the purpose of DS and ES registers? 2 marks

📄 Page 25 | Pattern: Register (85% likely)

DS: Data segment - holds data address

ES: Extra segment - holds string destination

Register	Full Name	Purpose
DS	Data Segment	Holds starting address of data segment. Most data access uses DS as default segment.
ES	Extra Segment	Used as additional data segment. String destination instructions use ES:DI combination.

💡 Note: DS is used for source in most instructions. ES is used for destination in string operations (MOVS, CMPS, etc.)

3a What is pipelining? How does 8086 achieve it? 2 marks

📄 Page 16 | Pattern: Queue (85% likely)

Pipelining: Fetching next instruction while current executes.

8086 uses 6-byte FIFO queue in BIU.

3b Evaluate: MOV AX, 1234H / MOV BX, AX / ADD AX, BX / SUB AX, 1111H 5 marks

📄 Page 8-9 | Pattern: Eval (85% likely)

Step	AX	BX
MOV AX, 1234H	1234H	-
MOV BX, AX	1234H	1234H
ADD AX, BX	2468H	1234H
SUB AX, 1111H	1357H	1234H

MOV AX, 1234H      ; AX = 1234H
MOV BX, AX         ; BX = 1234H
ADD AX, BX         ; AX = 1234H + 1234H = 2468H
SUB AX, 1111H      ; AX = 2468H - 1111H = 1357H

Step	Instruction	AX	BX
1	MOV AX, 1234H	1234H	-
2	MOV BX, AX	1234H	1234H
3	ADD AX, BX	2468H	1234H
4	SUB AX, 1111H	1357H	1234H

Final: AX = 1357H

💡 Hex Arithmetic: 1234H + 1234H = 2468H, then 2468H - 1111H = 1357H

3c Compare PUSH and POP operations 3 marks

📄 Page 19-22 | Pattern: Compare (75% likely)

Feature	PUSH	POP
SP Change	SP - 2	SP + 2
Data Flow	Reg → Stack	Stack → Reg

Feature	PUSH	POP
Operation	Store to stack	Read from stack
SP Change	SP = SP - 2 (decrement)	SP = SP + 2 (increment)
Data Flow	Register → Memory [SS:SP]	Memory [SS:SP] → Register
Stack Growth	Grows downward (toward lower addresses)	Shrinks upward (toward higher addresses)

💡 Remember: Stack grows downward - PUSH decrements SP, POP increments SP. Word (2 bytes) at a time.

4a Explain the function of AD15-AD0, ALE, BHE/S7, and RD pins of 8086 3 marks

📄 Micro-3 Page 7-9 | Pattern: Pins (75% likely)

Pin(s)	Function
AD15-AD0	Multiplexed Address/Data bus (16-bit)
ALE	Address Latch Enable - latches address
BHE/S7	Bus High Enable / Status bit 7
RD	Read control signal (active low)

Pin(s)	Type	Function
`AD15-AD0`	Multiplexed I/O	Time-multiplexed address (T1) and data (T2-T4) bus. ALE latches the address before data phase.
`ALE`	Output	Pulse in T1 state to latch valid address from AD bus into external latches (74LS373).
`BHE/S7`	Output	Active low during T1 to enable high byte of data bus. S7 is a status signal in later cycles.
`RD`	Output	Active low read strobe. CPU reads data from memory or I/O when RD=0. Used with IO/M̄ to select memory vs I/O.

💡 Key: AD bus is multiplexed to save pins. ALE must be used with external latches to separate address from data.

4b Compare minimum mode and maximum mode of 8086 2 marks

📄 Micro-3 Page 2-3, 12-16 | Pattern: Modes (75% likely)

Feature	Minimum Mode	Maximum Mode
Pin	MN/MX̄ = 1 (VCC)	MN/MX̄ = 0 (GND)
Control	8086 generates control signals	8288 bus controller generates signals
Multi-CPU	Single processor	Supports coprocessors

Feature	Minimum Mode	Maximum Mode
MN/MX̄ Pin	Tied to VCC (+5V)	Tied to GND
Control Signals	Directly from 8086: RD̄, WR̄, IO/M̄, ALE, DEN̄, DT/R̄	From 8288: MRDC̄, MWTC̄, IORC̄, IOWC̄, AIOWC̄
Bus Request	HOLD / HLDA	RQ̄/GT̄₀, RQ̄/GT̄₁ (request/grant)
Interrupt	INTR, INTA̅	INTR, INTA̅, QS₀, QS₁ (queue status)
Multi-CPU	Single processor only	Supports 8087/8089 coprocessors

💡 Key: Max mode uses 8288 for bus control and supports coprocessors. Min mode is simpler, used for single-processor systems.

4c Explain the S3/S4 segment decoding table and the RQ/GT DMA mechanism 5 marks

📄 Micro-3 Page 8, 15 | Pattern: Segments/DMA (70% likely)

S3/S4 Segment Decode Table:

S4	S3	Segment
0	0	ES
0	1	SS
1	0	CS / IP (prefetch)
1	1	DS

RQ/GT: Request/Grant signals for DMA bus access.

S3/S4 Segment Decoding Table: These status pins appear on AD15-AD12 during T1 to identify which segment register is being accessed.

S4	S3	Segment	Description
0	0	ES	Extra Segment access
0	1	SS	Stack Segment access
1	0	CS / IP	Code Segment or IP (prefetch queue)
1	1	DS	Data Segment access

RQ/GT (Request/Grant) DMA Mechanism:

Used in Maximum Mode for bus arbitration between 8086 and DMA controller:

DMA controller asserts RQ̄/GT̄ (active low) to request bus
8086 completes current bus cycle, then floats address/data/control bus
8086 sends GT̄ (grant) pulse on RQ̄/GT̄ to acknowledge
DMA controller takes bus control, performs transfers
DMA releases bus by asserting RQ̄ again → 8086 regains control

💡 Key: S3/S4 let external hardware identify the active segment. RQ/GT provides faster bus arbitration than HOLD/HLDA in min mode.

5a Draw the block diagram of 8254 and explain its components 3 marks

📄 Micro-3 Page 23-25 | Pattern: 8254 (75% likely)

8254 Components:

3 independent 16-bit down counters (Counter 0, 1, 2)
Data Bus Buffer (D7-D0)
Read/Write Logic (RD̄, WR̄, CS̄, A1, A0)
Control Word Register

8254 Block Diagram Components:

Data Bus Buffer: Bidirectional 8-bit buffer (D7-D0) connects to CPU data bus
Read/Write Logic: CS̄ (chip select), RD̄ (read), WR̄ (write), A1-A0 (counter select)
Control Word Register: Stores mode/format configuration written by CPU
Counter 0, 1, 2: Independent 16-bit programmable counters with CLK and OUT pins

Address Selection (A1, A0):

A1	A0	Selects
0	0	Counter 0
0	1	Counter 1
1	0	Counter 2
1	1	Control Word Register

💡 Key: Each counter has CLK (clock input), GATE (control input), and OUT (output) pins. The GATE input enables/disables counting.

5b Compare all six modes of 8254 timer 3 marks

📄 Micro-3 Page 30-36 | Pattern: 8254 Modes (75% likely)

Mode	Name	OUT Behavior
0	Interrupt on Terminal Count	Goes LOW on terminal count
1	Programmable One-Shot	Goes LOW for one CLK cycle
2	Rate Generator	Goes LOW for one CLK, then HIGH
3	Square Wave	50% duty cycle square wave
4	Software Triggered Strobe	Goes LOW for one CLK on count
5	Hardware Triggered Strobe	Goes LOW on GATE trigger

Mode	Name	Trigger	OUT Behavior	RETRIG
0	Interrupt on Terminal Count	Writing count	OUT goes LOW when count reaches 0; stays LOW until reloaded	No
1	Programmable One-Shot	GATE rising edge	OUT goes LOW for (N) CLK cycles then HIGH	Yes
2	Rate Generator	Writing count	OUT goes LOW for 1 CLK every N CLKs (N-1 HIGH)	No
3	Square Wave	Writing count	OUT toggles: ⌊N/2⌉ HIGH, ⌈N/2⌉ LOW (50% duty)	No
4	Software Triggered Strobe	Writing count	OUT goes LOW for 1 CLK when count reaches 0	No
5	Hardware Triggered Strobe	GATE rising edge	OUT goes LOW for 1 CLK after N CLKs from trigger	Yes

💡 Key: Modes 0,2,3,4 are software-triggered. Modes 1,5 are hardware-triggered via GATE. Mode 3 is most used for baud rate/square wave generation.

5c Explain the 8254 control word format and write a program to initialize Counter 0 in Mode 3 (square wave) with count 5000 4 marks

📄 Micro-3 Page 26 | Pattern: 8254 Control Word (75% likely)

Control Word (SC1 SC0 RL1 RL0 M2 M1 M0 BCD):

Bit	7-6	5-4	3-1	0
Name	SC (Select)	RL (Read/Load)	M (Mode)	BCD
Values	00=C0, 01=C1, 10=C2, 11=Ctrl	00=Latch, 01=LSB, 10=MSB, 11=LSB+MSB	000-101	0=binary, 1=BCD

; Counter 0, Mode 3, 16-bit binary, count=5000
MOV AL, 36H       ; Control word: SC=00, RL=11, M=011, BCD=0
OUT 0E6H, AL      ; Write control word to control register
MOV AX, 5000      ; Count value
OUT 0E0H, AL      ; Write LSB to Counter 0
MOV AL, AH
OUT 0E0H, AL      ; Write MSB to Counter 0

8254 Control Word Format:

Bit	7	6	5	4	3	2	1	0
Name	SC1 SC0		RL1 RL0		M2 M1 M0			BCD
Desc	Counter Select		Read/Load		Mode Select			0=BIN, 1=BCD

SC (7-6): 00=Counter0, 01=Counter1, 10=Counter2, 11=Read-Back Command
RL (5-4): 00=Latch, 01=LSB only, 10=MSB only, 11=LSB then MSB
M (3-1): 000=Mode0, 001=Mode1, 010=Mode2, 011=Mode3, 100=Mode4, 101=Mode5
BCD (0): 0=16-bit binary, 1=4-digit BCD

Control Word for Counter 0, Mode 3, 16-bit Binary:

SC=00, RL=11 (16-bit), M=011 (Mode 3), BCD=0 (binary)
Binary: 00 11 011 0 = 0011 0110 = 36H

Program (Counter 0 at base port 0E0H, control at 0E6H):

; Initialize Counter 0 in Mode 3, count = 5000, binary
MOV AL, 36H       ; Control word: 00 11 011 0 = 36H
OUT 0E6H, AL      ; Send control word to 8254

MOV AX, 5000      ; Count value (5000 = 1388H)
OUT 0E0H, AL      ; Write LSB (88H) to Counter 0
MOV AL, AH        ; AL = 13H
OUT 0E0H, AL      ; Write MSB (13H) to Counter 0

; OUT pin of Counter 0 now generates square wave
; Frequency = CLK_in / 5000

💡 Key: Control word must be written before initializing counter. For 16-bit count, RL=11 means write LSB first, then MSB. Mode 3 produces 50% duty cycle square wave.

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